RC delays are used to introduce a lag in the behavior of high speed signals such as SPI clock, Ethernet lines emmc lines etc. Some times RC are put in the circuit to have control over reflections and also to have minimum over shoot and undershoot.
To calculate delay inserted in the digital line,say SPI clock , for example, if a series resistance have been used of value 33 ohm and a capacitor near the clock input pin of slave SPI ( who receives the clock) of value 47 pf which are normal to see in many boards.. Delay is
5 * RC,
= 5 * 33 * 47
=~7.5 ns
it should be read as: SPI clock now takes an extra of 7.5 ns to reach low to high compared to previous case.
it follows from the same way that while reaching low the signal will take 7.5 ns more.. Some times, this will have impact on maximum operating frequency.. Too much RC is also not good as it increased the signal's include state for more duration causing more power consumption. There should be nice balance between minimum rc for signal integrity and maximum required operating frequency.
To calculate delay inserted in the digital line,say SPI clock , for example, if a series resistance have been used of value 33 ohm and a capacitor near the clock input pin of slave SPI ( who receives the clock) of value 47 pf which are normal to see in many boards.. Delay is
5 * RC,
= 5 * 33 * 47
=~7.5 ns
it should be read as: SPI clock now takes an extra of 7.5 ns to reach low to high compared to previous case.
it follows from the same way that while reaching low the signal will take 7.5 ns more.. Some times, this will have impact on maximum operating frequency.. Too much RC is also not good as it increased the signal's include state for more duration causing more power consumption. There should be nice balance between minimum rc for signal integrity and maximum required operating frequency.
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